Toshiba develops 40nm semiconductor design tool

Toshiba Corp. has developed a simulation tool that can help improve yield when manufacturing semiconductor devices with a 40nm design rule. To improve the performance of transistors fabricated with 40nm circuit widths, the silicon wafer is subjected to high pressure and then instantly heated to around 1,000 C. During heating, the silicon expands, which can cause tiny crystal fissures and other defects that lower the yield of good chips.

Toshiba has developed software to simulate the process and predict the occurrence of crystal defects. With this information in hand, the transistors can be redesigned and the simulation run again and again until the defect rate is reduced and the yield boosted to nearly 100 percent. Using this software, Toshiba was able to determine that almost no crystal defects would occur if the surface area of the silicon-germanium pushing against the silicon in the transistor was reduced by 78 percent. The company calculates that 40nm SRAM could be made with a 100 percent yield by introducing this design change.

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